View CAT9532YI-T2_7327370.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

cat9532 ? catalyst semiconductor, inc. 1 doc. no. md-9001 rev. c characteristics subject to change without notice 16-bit programmable led dimmer with i 2 c interface features ? 16 led drivers with dimming control ? 256 brightness steps ? 16 open drain outputs drive 25 ma each ? 2 selectable programmable blink rates: ? frequency: 0.593hz to 152hz ? duty cycle: 0% to 99.6% ? i/os can be used as gpios ? 400khz i 2 c bus compatible* ? 2.3v to 5.5v operation ? 5v tolerant i/os ? active low reset input ? rohs-compliant 24-lead soic, tssop and 24-pad tqfn (4 x 4mm) packages applications ? backlighting ? rgb color mixing ? sensors control ? power switches, push-buttons ? alarm systems description the cat9532 is a cmos devic e that provides 16-bit parallel input/output port expander optimized for led dimming control. the cat9532 outputs can drive directly 16 leds in parallel. each individual led may be turned on, off, or blinking at one of two programmable rates. the device provides a simple solution for dimming leds in 256 brightness steps for backlight and color mixing applications. the cat9532 is suitable in i 2 c and smbus compatible applications where it is necessary to limit the bus traffic or free-up the bus master?s timer. the cat9532 contains an internal oscillator and two pwm signals that drive the led outputs. the user can program the period and duty cycle for each individual pwm signal. after the initial set-up command to program the blink rate 1 and blink rate 2 (frequency and duty cycle), only one command from the bus master is required to turn each individual open drain output on, off, or cycle at blink rate 1 or blink rate 2. each open drain led output can provide a maximum output current of 25ma. the total curr ent sunk by all i/os must not exceed 200ma. typical application circuit for ordering information details, see page 16. notes: led0 to led11 are used as led drivers led12 to led15 are used as regular gpios * catalyst semiconductor is licensed by philips corporation to carry the i 2 c protocol. cat9532 gpios i 2 c/smbus master v ss a0 a1 a2 rs0 3 x 10k rs1 rs11 5 v led11 led1 led0 v cc led12 led15 sda 5 v scl sda scl reset reset
cat9532 doc. no. md-9001 rev. c 2 ? catalyst semiconductor, inc. characteristics subject to change without notice pin configuration soic (w) , tssop (y) tqfn (hv6) 1 2 3 4 5 6 24 23 22 21 20 19 reset led15 led14 led13 led12 led11 7 8 9 10 11 12 18 17 16 15 14 13 led0 led1 led2 led3 led4 led5 led6 led7 v ss led8 led9 led10 a2 a1 a0 v cc sda scl pin description dip / soic / tssop tqfn pin name function 1 22 ao address input 0 2 23 a1 address input 1 3 24 a2 address input 2 4-11 1-8 led0 - led7 led driver output 0 to 7, i/o port 0 to 7 12 9 v ss ground 13-20 10-17 led8 - led15 led driver output 8 to 15, i/o port 8 to 15 21 18 reset reset input 22 19 scl serial clock 23 20 sda serial data 24 21 v cc power supply block diagram v cc reset scl a2 a1 a0 sda ledx v ss input filters power on reset oscillator prescaler 0 register prescaler 1 register pwm 0 register led select (lsx) register input register blink 0 cat9532 blink 1 control logic pwm 1 register note: only one i/o is shown for clarity i 2 c bus control 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 19 17 16 15 14 13 ao a1 a2 led0 led1 led2 led3 led4 led5 led6 led7 v ss v cc sda scl reset led15 led14 led13 led12 led11 led10 led9 led8
cat9532 ? catalyst semiconductor, inc. 3 doc. no. md-9001 rev. c characteristics subject to change without notice absolute maximum ratings (1) parameters ratings units v cc with respect to ground -2.0 to +7.0 v voltage on any pin with respect to ground -0.5 to +5.5 v dc current on i/os 25 ma supply current 200 ma package power dissipation capability (t a = 25oc) 1.0 w junction temperature +150 c storage temperature -65 to +150 oc lead soldering temperature (10 seconds) 300 oc operating ambient temperature -40 to +85 oc notes: (1) stresses above those listed under ?absol ute maximum ratings? may cause permanent damage to the device. these are stress ra tings only, and functional operation of the device at these or any ot her conditions outside of those lis ted in the operational sectio ns of this specification is not implied. exposure to any absolute maximum rating for extended pe riods may affect device performance and re liability.
cat9532 doc. no. md-9001 rev. c 4 ? catalyst semiconductor, inc. characteristics subject to change without notice d.c. operating characteristics v cc = 2.3 to 5.5v, v ss = 0v; t a = -40oc to +85oc, unless otherwise specified symbol parameter conditions min typ max unit supplies v cc supply voltage 2.3 ? 5.5 v i cc supply current operating mode; v cc = 5.5v; no load; f scl = 100khz ? 250 550 a i stb standby current standby mode; v cc = 5.5v; no load; v i = v ss or v cc , f scl = 0khz ? 2.1 5.0 a i stb additional standby current standby mode; v cc = 5.5v; every led i/o = v in = 4.3v, f scl = 0khz ? ? 2 ma v por (1) power-on reset voltage v cc = 3.3v, no load; v i = v cc or v ss ? 1.5 2.2 v scl, sda, reset v il (2) low level input voltage -0.5 ? 0.3 v cc v v ih (2) high level input voltage 0.7 v cc ? 5.5 v i ol low level output current v ol = 0.4v 3 ? ? ma i il leakage current v i = v cc = v ss -1 ? +1 a c i (3) input capacitance v i = v ss ? ? 6 pf c o (3) output capacitance v o = v ss ? ? 8 pf a0, a1, a2 v il (2) low level input voltage -0.5 ? 0.8 v v ih (2) high level input voltage 2.0 ? 5.5 v i il input leakage current -1 ? 1 a i/os v il (2) low level input voltage -0.5 ? 0.8 v v ih (2) high level input voltage 2.0 ? 5.5 v v ol = 0.4v; v cc = 2.3v 9 ? ? v ol = 0.4v; v cc = 3.0v 12 ? ? v ol = 0.4v; v cc = 5.0v 15 ? ? v ol = 0.7v; v cc = 2.3v 15 ? ? v ol = 0.7v; v cc = 3.0v 20 ? ? i ol (4) low level output current v ol = 0.7v; v cc = 5.0v 25 ? ? ma i il input leakage current v cc = 3.6v; v i = v ss or v cc -1 ? 1 a c i/o (3) input/output capacitance ? ? 8 pf notes: (1) v dd must be lowered to 0.2v in order to reset the device. (2) v il min and v ih max are reference values only and are not tested. (3) this parameter is characterized init ially and after a design or process change that affects the parameter. not 100% tested. (4) the output current must be limited to a maximum 25ma per each i/o; the total current sunk by all i/o must be limited to 200 ma (or 100ma for eight i/os)
cat9532 ? catalyst semiconductor, inc. 5 doc. no. md-9001 rev. c characteristics subject to change without notice a.c. characteristics v cc = 2.3v to 5.5v, t a = -40oc to +85oc, unless otherwise specified (1) symbol parameter min typ max units f scl clock frequency 400 khz t sp (2) input filter spike suppression (sda, scl) 50 ns t low clock low period 1.3 s t high clock high period 0.6 s t r (2) sda and scl rise time 300 ns t f (2) sda and scl fall time 300 ns t hd:sta start condition hold time 0.6 s t su:sta start condition setup time (for a repeater start) 0.6 s t hd:dat data input hold time 0 ns t su:dat data in setup time 100 ns t su:sto stop condition setup time 0.6 s t aa scl low to data out valid 900 ns t dh data out hold time 50 ns t buf (2) time the bus must be free before a new transmission can start 1.3 s port timing t pv output data valid 200 ns t ps input data setup time 100 ns t ph input data hold time 1 s reset t w (2) reset pulse width 10 ns t rec reset recovery time 0 ns t reset (3) time to reset 400 ns notes: (1) test conditions according to "ac test conditions" table. (2) this parameter is characterized init ially and after a design or process change that affects the parameter. not 100% tested. (3) the full delay to reset the part will be the sum of t reset and the rc time constant of the sda line.
cat9532 doc. no. md-9001 rev. c 6 ? catalyst semiconductor, inc. characteristics subject to change without notice ac test conditions input pulse voltage 0.2v cc to 0.8v cc input rise and fall times 5ns input reference voltage 0.3v cc , 0.7v cc output reference voltage 0.5v cc output load current source: i ol = 3ma; 400pf for f scl(max) = 400khz figure 1. 2-wire serial interface timing pin description scl: serial clock the serial clock input clocks all data transferred into or out of the device. the scl line requires a pull-up resistor if it is driven by an open drain output. sda: serial data/address the bidirectional serial data/address pin is used to transfer all data into and out of the device. the sda pin is an open drain output and can be wire-ored with other open drain or open collector outputs. a pull- up resistor must be connected from sda line to v cc . led0 to led15: led driver outputs / general purpose i/os the pins are open drain outputs used to drive directly leds. any of these pins can be programmed to drive the led on, off, blink rate1 or blink rate2. when not used for controlling the leds, these pins may be used as general purpose parallel input/output. reset : external reset input active low reset input is used to initialize the cat9532 internal registers and the i 2 c state machine. the internal registers are held in their default state while reset input is active. an external pull-up resistor of maximum 25k ? is required when this pin is not actively driven. t high scl sda in sda out t low t f t low t r t buf t su:sto t su:dat t hd:dat t hd:sta t su:sta t aa t dh
cat9532 ? catalyst semiconductor, inc. 7 doc. no. md-9001 rev. c characteristics subject to change without notice functional description the cat9532 is a 16-bit i/o bus expander that provides a programmable led dimmer, controlled through an i 2 c compatible serial interface. the cat9532 supports the i 2 c bus data transmission protocol. this inter-integrated circuit bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. the transfer is controlled by the master device which generates the serial clock and all start and stop conditions for bus access. the cat9532 operates as a slave device. both the master device and slave devic e can operate as either transmitter or receiver, but the master device controls which mode is activated. i 2 c bus protocol the features of the i 2 c bus protocol are defined as follows: (1) data transfer may be initiated only when the bus is not busy. (2) during a data transfer, the data line must remain stable whenever the clock line is high. any changes in the data line while the clock line is high will be interpreted as a start or stop condition (figure 2). start and stop conditions the start condition precedes all commands to the device, and is defined as a high to low transition of sda when scl is high. the cat9532 monitors the sda and scl lines and will not respond until this condition is met. a low to high transition of sda when scl is high determines the stop condition. all operations must end with a stop condition. device addressing after the bus master sends a start condition, a slave address byte is requi red to enable the cat9532 for a read or write operation. the four most significant bits of the slave address are fixed as binary 1100 (figure 3). the cat9532 uses the next three bits as address bits. the address bits a2, a1 and a0 are used to select which device is accessed from maximum eight devices on the same bus. these bits must compare to their hardwired input pins. the 8th bit following the 7- bit slave address is the r/w bit that specifies whether a read or write operation is to be performed. when this bit is set to ?1?, a read operation is initiated, and when set to ?0?, a write operation is selected. following the start condition and the slave address byte, the cat9532 monitors the bus and responds with an acknowledge (on the sda line) when its address matches the transmitted slave address. the cat9532 then performs a read or a write operation depending on the state of the r/w bit. figure 2. start/stop timing figure 3. cat9532 slave address start condition sda stop condition scl 1 1 0 0 a2 a1 a0 r/w slave address fixed programmable hardware selectable
cat9532 doc. no. md-9001 rev. c 8 ? catalyst semiconductor, inc. characteristics subject to change without notice acknowledge after a successful data transfer, each receiving device is required to generate an acknowledge. the acknowledging device pulls down the sda line during the ninth clock cycle, signa ling that it received the 8 bits of data. the sda line remains stable low during the high period of the acknowledge related clock pulse (figure 4). the cat9532 responds with an acknowledge after receiving a start condition and its slave address. if the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8- bit byte. when the cat9532 begins a read mode it transmits 8 bits of data, releases the sda line, and monitors the line for an acknowledge. once it receives this acknowledge, the cat9532 will continue to transmit data. if no acknowledge is sent by the master, the device terminates data transmission and waits for a stop condition. the master must then issue a stop condition to return the ca t9532 to the standby power mode and place the device in a known state. registers and bus transactions after the successful ack nowledgement of the slave address, the bus master w ill send a command byte to the cat9532 which will be stored in the control register. the format of the control register is shown in figure 5. the control register acts as a pointer to determine which register will be writt en or read. the four least significant bits, b0, b1, b2, b3, are used to select which internal register is accessed, according to the table 1. if the auto increment flag (ai) is set, the four least significant bits of the control register are automatically incremented after a read or write operation. this allows the user to access the cat9532 internal registers sequentially. the content of these bits will rollover to ?0000? after the last register is accessed. table 1. internal registers selection b3 b2 b1 b0 register name type register function 0 0 0 0 input0 read input register 0 0 0 0 1 input1 read input register 1 0 0 1 0 psc0 read/ write frequency prescaler 0 0 0 1 1 pwm0 read/ write pwm register 0 0 1 0 0 psc1 read/ write frequency prescaler 1 0 1 0 1 pwm1 read/ write pwm register 1 0 1 1 0 ls0 read/ write led 0-3 selector 0 1 1 1 ls1 read/ write led 4-7 selector 1 0 0 0 ls2 read/ write led 8-11 selector 1 0 0 1 ls3 read/ write led 12-15 selector figure 4. acknowledge timing figure 5. control register acknowledge 1 start scl from master 89 data output f r om transmitter data output from receiver 000ai b3 b2 b1 b0 auto-increment flag reset state: 00h register address
cat9532 ? catalyst semiconductor, inc. 9 doc. no. md-9001 rev. c characteristics subject to change without notice the input register 0 and input register 1 reflect the incoming logic levels of the i/o pins, regardless of whether the pin is defined as an input or an output. these registers are read only ports. writes to the input registers will be acknowledged but will have no effect. table 2. input register 0 and input register 1 input0 led 7 led 6 led 5 led 4 led 3 led 2 led 1 led 0 bit 7 6 5 4 3 2 1 0 default x x x x x x x x input1 led 15 led 14 led 13 led 12 led 11 led 10 led 9 led 8 bit 7 6 5 4 3 2 1 0 default x x x x x x x x the frequency prescaler 0 and frequency prescaler 1 registers (psc0, psc1) are used to program the period of the pulse width modulated signals blink0 and blink1 respectively: t_blink0 = (psc0 + 1) / 152; t_blink1 = (psc1 + 1) / 152 table 3. frequency prescaler 0 and frequency prescaler 1 registers psc0 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 psc1 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 the pwm register 0 and pwm register 1 (pwm0, pwm1) are used to program the duty cycle of blink0 and blink1 respectively: duty cycle_blink0 = pwm0 / 256; duty cycle_blink1 = pwm1 / 256 after writing to the pwm0/1 register an 8-bit internal counter starts to count from 0 to 255. the outputs are low (led on) when the counter value is less than the value programmed into pwm register. the led is off when the counter value is higher than the value written into pwm register. table 4. pwm register 0 and pwm register 1 pwm0 bit 7 6 5 4 3 2 1 0 default 1 0 0 0 0 0 0 0 pwm1 bit 7 6 5 4 3 2 1 0 default 1 0 0 0 0 0 0 0 every led driver output can be programmed to one of four states, led off, led on, led blinks at blink0 rate and led blinks at blink1 rate using the led selector registers (table 5). table 5. led selector registers ls0 led 3 led 2 led 1 led 0 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 ls1 led 7 led 6 led 5 led 4 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 ls2 led 11 led 10 led 9 led 8 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 ls3 led 15 led 14 led 13 led 12 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 the led output (led0 to led15) is set by the 2 bits value from the corresponding lsx register (x = 0 to 3): 00 = led output set hi-z (led off ? default) 01 = led output set low (led on) 10 = led output blinks at blink0 rate 11 = led output blinks at blink1 rate
cat9532 doc. no. md-9001 rev. c 10 ? catalyst semiconductor, inc. characteristics subject to change without notice write operations data is transmitted to the cat9532 registers using the write sequence shown in figure 6. if the ai bit from the command byte is set to ?1?, the cat9532 internal registers can be written sequentially. after sending data to one register, the next data byte will be sent to the next register sequentially addressed. read operations the cat9532 registers are read according to the timing diagrams shown in fi gure 7 and figure 8. data from the register, defined by the command byte, will be sent serially on the sda line. after the first byte is read, additional data bytes may be read when the auto-increment flag, ai, is set. the additional data byte will reflect the data read from the next register sequentially addr essed by the (b3 b2 b1 b0) bits of the command byte. when reading input port registers (figure 8), data is clocked into the register on the failing edge of the acknowledge clock pulse. the transfer is stopped when the master will not ac knowledge the data byte received and issue the stop condition. led pins used as general purpose i/o any led pins not used to drive leds can be used as general purpose input/output, gpio. when used as input, the user should program the corresponding led pin to hi-z (?00? for the lsx register bits). the pin state can be read via the input register according to the sequence shown in figure 8. for use as output, an external pull-up resistor should be connected to the pin. the value of the pull-up resistor is calculated according to the dc operating characteristics. to set th e led output high, the user has to program the output hi-z writing ?00? into the corresponding led selector (lsx) register bits. the output pin is set low when the led output is programmed low through the lsx register bits (?01? in lsx register bits). figure 6. write to register timing diagram figure 7. read from register timing diagram 12 scl write to register data out from port 345678 sda a slave address data to register 1 start condition r/w acknowledge from slave acknowledge from slave acknowledge from slave 9 command byte 1.0 a data to register 2 s 1 1 0 0 a2 a1 a0 0 t pv a a ai b3 b2 b1 b0 a 000 dat 1 s a 0 0 a2 a1 a0 1 1 0 0 a2 a1 a0 1 1 a a command byte acknowledge from slave acknowledge from slave a p na acknowledge from slave acknowledge from master s data data r/w first byte last byte no acknowledge from master 1 slave address data from register data from register slave address msb lsb msb lsb 0 note: transfer can be stopped at any time by a stop condition. r/w at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter auto-increment register address if al = 1
cat9532 ? catalyst semiconductor, inc. 11 doc. no. md-9001 rev. c characteristics subject to change without notice external reset operation the cat9532 registers and the i 2 c state machine are initialized to their default state when the reset input is held low for a minimum of t w . the external reset timing is shown in figure 9. power-on reset operation the cat9532 incorporates power-on reset (por) circuitry which protects the internal logic against powering up in the wrong state. the device is in a reset state for v cc less than the internal por threshold level (v por ). when v cc exceeds the v por level, the reset state is released and the cat9532 internal state machine and registers are initialized to their default state. figure 8. read input port register timing diagram figure 9. reset timing diagram sda scl t reset t reset 50% 30% 50% 50% 50% t rec t w reset ledx led off ack or read cycle start 1 1 0 0 a2 a1 a0 read from port data into port sda saa data 1 data 4 slave address data from port data from port start condition r/w acknowledge from slave acknowledge from master stop condition t ps data 4 data 2 p data 3 t ph na data 1 no acknowledge from master
cat9532 doc. no. md-9001 rev. c 12 ? catalyst semiconductor, inc. characteristics subject to change without notice application information programming example the following programming sequence is an example how to set: ? led0 to led3: on ? led4 to led7: dimming at 30% brightness; blink 1: 152hz, duty cycle 30% ? led8 to led11: blink at 2hz with 50% duty cycle (blink 2) ? led12 to led15: off command description i 2 c data 1 start 2 send slave address, a0-a2 = low c0h 3 command byte: ai=?1?; psc0 addr 12h 4 set blink 1 at 152hz, t_blink1 = 1/152 write psc0 = 0 00h 5 set pwm0 duty cycle to 30% pwm0 / 256 = 0.3; write pwm0=77 4dh 6 set blink 2 at 2hz, t_blink1 = 1/2 write psc1 = 75 4bh 7 set pwm1 duty cycle to 50% pwm1 / 256 = 0.5; write pwm1=128 80h 8 write ls0: led0 to led3 = on 55h 9 write ls1: led4 to led7 at blink1 aah 10 write ls2: led8 to led11 at blink2 ffh 11 write ls3: led12 to led15 = off 00h 12 stop figure 10. typical application 5v 5v led0 led1 led2 led3 led4 led5 led6 led7 led8 led9 led10 led11 led12 led13 led14 led15 a2 a1 a0 v ss sda v cc v cc scl cat9532 reset reset sda scl gnd i 2 c/smbus master 10k ? (x 3) gpios note: led0 to led11 are used as led drivers and led12 to led15 are used as regular gpios.
cat9532 ? catalyst semiconductor, inc. 13 doc. no. md-9001 rev. c characteristics subject to change without notice package outline drawings soic 24-lead (w) (1)(2) notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec ms-013. for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf. e1 e a1 a2 e pin#1 identification b d c a top view side view end view 1 1 h h l symbol min nom max a2.35 2.65 a1 0.10 0.30 a2 2.05 2.55 b0.31 0.51 c0.20 0.33 d 15.20 15.40 e 10.11 10.51 e1 7.34 7.60 e 1.27 bsc h0.25 0.75 l0.40 1.27 0 8 1 5 15
cat9532 doc. no. md-9001 rev. c 14 ? catalyst semiconductor, inc. characteristics subject to change without notice tssop 24-lead 4.4mm (y) (1)(2) notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec mo-153. for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf. 1 a 1 a2 d top view side view end view e e1 e b l1 c l a symbol min nom max a1.20 a1 0.05 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 7.70 7.80 7.90 e 6.25 6.40 6.55 e1 4.30 4.40 4.50 e 0.65 bsc l 1.00 ref l1 0.50 0.60 0.70 10 8
cat9532 ? catalyst semiconductor, inc. 15 doc. no. md-9001 rev. c characteristics subject to change without notice tqfn 24-lead 4 x 4mm (hv6) (1)(2) notes: (1) all dimensions are in millimeters. (2) complies with jedec standard mo-220. for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf. e2 e b a side view top view bottom view e d pin#1 index area pin#1 id front view detail a a1 a l detail a d2 a3 symbol min nom max a 0.70 0.75 0.80 a1 0.00 0.02 0.05 a3 0.20 ref b 0.18 0.25 0.30 d 3.90 4.00 4.10 d2 2.40 ? 2.90 e 3.90 4.00 4.10 e2 2.40 ? 2.90 e 0.50 bsc l 0.30 0.40 0.50
cat9532 doc. no. md-9001 rev. c 16 ? catalyst semiconductor, inc. characteristics subject to change without notice example of ordering information (1) ordering part number part number package lead finish cat9532wi soic matte-tin cat9532wi-t1 soic matte-tin cat9532yi tssop matte-tin CAT9532YI-T2 tssop matte-tin cat9532hv6i-g tqfn nipdau cat9532hv6i-gt2 tqfn nipdau notes: (1) all packages are rohs-compliant (lead-free, halogen-free). (2) the standard plated finish is matte-tin for soic and tssop packages. the standard plated finish is nipdau for tqfn package. (3) the device used in the above example is a cat9532wi-t1 (soic, industrial temperature, matte-tin, tape & reel). (4) for additional temperature options , please contact your nearest cataly st semiconductor sales office. prefix device # suffix cat 9532 w i ? gt1 company id product numbe r 9532 temperature range i = industrial (-40oc to 85oc) package w: soic, jedec y: tssop hv6: t q fn tape & reel t: tape & reel 1: 1000/reel soic only 2: 2000/reel lead finish blank: matte-tin g: nipdau for product top mark codes, click here: http://www.catsemi.com/techsupport/producttopmark.asp
revision history date rev. reason 10/23/07 a initial issue 12/07/07 b update example of ordering information and ordering part number 04/16/08 c delete tqfn package in matte-tin update package outline drawing ? tqfn 24-pad 4 x 4mm catalyst semiconductor, inc. corporate headquarters 2975 stender way santa clara, ca 95054 phone: 408.542.1000 document no: md-9001 fax: 408.542.1200 revision: c www.catsemi.com issue date: 04/16/08 copyrights, trademarks and patents ? catalyst semiconductor, inc. trademarks and register ed trademarks of catalyst semiconductor include each of the following: adaptive analog?, beyond memory?, dpp?, ezdim?, ldd?, minipot?, quad-mode? and quant um charge programmable? catalyst semiconductor has been issued u. s. and foreign patents and has patent applicat ions pending that protect its products. catalyst semiconductor makes no warranty, representation or guar antee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its pro ducts will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semiconduct or product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any produ ct or service descr ibed herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in pr oduction or offered for sale. catalyst semiconductor advises customers to obtain the current version of the rele vant product informati on before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete.

▲Up To Search▲

Price & Availability of CAT9532YI-T2

	To Download CAT9532YI-T2 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .